1. Field of the Invention
The present invention relates to a variable-gain amplifier, i.e., an amplifier that permits its gain to be controlled, for use in an integrated circuit, and more particularly to a variable-gain amplifier for use in an integrated circuit for receiving digital satellite broadcasts.
2. Description of the Prior Art
FIG. 16 shows an example of the configuration of a conventional variable-gain amplifier. An input voltage signal VIN1 is fed to a terminal that is connected to the base of an NPN-type input transistor Q1, and an input voltage signal VIN2 is fed to a terminal that is connected to the base of an NPN-type input transistor Q2. The emitters of the input transistors Q1 and Q2 are connected together through a resistor RE1. The emitter of the input transistor Q1 is grounded through a constant current source 1 that outputs a constant current IC, and the emitter of the input transistor Q2 is grounded through a constant current source 2 that outputs a constant current IC.
To the collector of the input transistor Q1, the emitters of NPN-type transistors Q3 and Q4 are connected. To the collector of the input transistor Q2, the emitters of NPN-type transistors Q5 and Q6 are connected.
A constant voltage VCC is supplied to a terminal that is connected to one end of a resistor RL1, to the collector of the transistor Q4, to the collector of the transistor Q5, and to one end of a resistor RL2. The other end of the resistor RL1 is connected to the collector of the transistor Q3 and to a terminal from which an output voltage signal VOUT1 is fed out, and the other end of the resistor RL2 is connected to the collector of the transistor Q6 and to a terminal from which an output voltage signal VOUT2 is fed out.
A reference voltage VB1 is supplied to a terminal that is connected to the base of the transistor Q3 and to the base of the transistor Q6. A control voltage VC1 is supplied to a terminal that is connected to the base of the transistor Q4 and to the base of the transistor Q5.
Next, the operation of the variable-gain amplifier of FIG. 16 will be described. When the levels of the input voltage signals VIN1 and VIN2 are low, the control voltage VC1 is reduced so that the base potential of the transistors Q3 and Q6 is higher than the base potential of the transistors Q4 and Q5. As a result, almost no current flows through the transistors Q4 and Q5, and most of the collector current of the input transistors flows through the transistors Q3 and Q6. Accordingly, a large amount of current flows through the output load resistors RL1 and RL2, yielding a high gain.
On the other hand, when the levels of the input voltage signals VIN1 and VIN2 are high, the control voltage VC1 is increased so that the base potential of the transistors Q3 and Q6 is lower than the base potential of the transistors Q4 and Q5. As a result, most of the collector current of the input transistors flows through the transistors Q4 and Q5, and almost no current flows through the transistors Q3 and Q6. Accordingly, a small amount of current flows through the output load resistors RL1 and RL2, yielding a low gain. Thus, the gain characteristic curve T1 of the variable-gain amplifier of FIG. 16 with respect to the control voltage VC1 is as shown in FIG. 17. In FIG. 17, the symbol Vth1 represents the threshold level of the control voltage VC1 at which the variable-gain amplifier of FIG. 16 starts attenuating its gain.
When the variable-gain amplifier is used in a digital satellite broadcast system or terrestrial broadcast system, the input voltage signals VIN1 and VIN2 are high-frequency signals having frequencies of from about a few hundred MHz to a few GHz. Moreover, in a digital satellite broadcast system or terrestrial broadcast system, a wide dynamic range of typically 60 dB or over is required.
However, in the variable-gain amplifier of FIG. 16, when high-frequency signals are fed in, leak current flows through the collector-emitter parasitic capacitance (about a few tens of fF) of the transistors Q3 and Q6. This causes saturation of gain attenuation, and thus the gain characteristic curve T2 of the variable-gain amplifier with respect to the control voltage VC1 when high-frequency signals are fed in is as shown in FIG. 18.
In this way, the variable-gain amplifier of FIG. 16 cannot attenuate its gain sufficiently when high-frequency signals are fed in, and thus, quite inconveniently, does not offer a wide input dynamic range as required in a digital satellite broadcast system or terrestrial broadcast system.
FIG. 19 shows another example of the configuration of a conventional variable-gain amplifier. The variable-gain amplifier of FIG. 19 is provided with a variable-gain amplifier circuit A1 and a variable-gain amplifier circuit A2.
First, the configuration of the variable-gain amplifier circuit A1 will be described. An input signal Vin1 is fed to a terminal that is connected to the base of an NPN-type input transistor Q21, and an input signal Vin2 is fed to a terminal that is connected to the base of an NPN-type input transistor Q22. The emitters of the input transistors Q21 and Q22 are connected together through a resistor R7. The emitter of the input transistor Q21 is grounded through a constant current source 21 that produces a bias current IC, and the emitter of the input transistor Q22 is grounded through a constant current source 22 that produces a bias current IC.
To the collector of the input transistor Q21, the emitters of NPN-type transistors Q14 and Q15 are connected. To the collector of the input transistor Q22, the emitters of NPN-type transistors Q16 and Q17 are connected.
A constant voltage VCC is supplied to a terminal that is connected to the collectors of the transistors Q15 and Q16.
A bias voltage Vbias is supplied to a terminal that is connected to the bases of the transistors Q14 and Q17. A control voltage VAGC, which is a reference control voltage, is supplied to a terminal that is connected to the bases of the transistors Q15 and Q16.
Next, the configuration of the variable-gain amplifier circuit A2 will be described. The terminal to which the input signal Vin1 is fed is connected to the base of an NPN-type input transistor Q20, and the terminal to which the input signal Vin2 is fed is connected to the base of an NPN-type input transistor Q23. The emitters of the input transistors Q20 and Q23 are connected together through a resistor R8. The emitter of the input transistor Q20 is grounded through a constant current source 20 that produces a bias current IC, and the emitter of the input transistor Q23 is grounded through a constant current source 23 that produces a bias current IC.
To the collector of the input transistor Q20, the emitters of NPN-type transistors Q12 and Q13 are connected. To the collector of the input transistor Q23, the emitters of NPN-type transistors Q18 and Q19 are connected.
The terminal to which the constant voltage VCC is supplied is connected to one end of an output load resistor R5, to the collector of the transistor Q13, to the collector of the transistor Q18, and to one end of an output load resistor R6. The other end of the output load resistor R5 is connected to the collector of the transistor Q12, and the other end of the output load resistor R6 is connected to the collector of the input transistor Q19.
The terminal to which the bias voltage Vbias is supplied is connected to the bases of the transistors Q12 and Q19. The terminal to which the control voltage VAGC is supplied is connected through a resistor R3 to the bases of the transistors Q13 and Q18. The node between the resistor R3 and the transistors Q3 and Q8 is grounded through a resistor R4.
The variable-gain amplifier circuits A1 and A2 configured as described above are connected in parallel. Superficially, the collectors of the transistors Q12 and Q14 are both connected to a terminal from which an output signal Vout1 is fed out, and the collectors of the transistors Q17 and Q19 are both connected to a terminal from which an output signal Vout2 is fed out.
In the variable-gain amplifier circuits A1 and A2, there is a tradeoff between noise factor and intermodulation distortion characteristics. Therefore, the variable-gain amplifier circuit A1 is designed to offer good noise factor characteristics, and the variable-gain amplifier circuit A2 is designed to offer good intermodulation distortion characteristics.
Next, the operation of the variable-gain amplifier of FIG. 19 will be described. When the levels of the input signals Vin1 and Vin2 are low, the control voltage VAGC is reduced so that the base potential of the transistors Q12, Q14, Q17, and Q19 is higher than the base potential of the transistors Q13, Q15, Q16, and Q18. As a result, almost no current flows through the transistors Q13, Q15, Q16, and Q18, and most of the collector current of the input transistors flows through the transistors Q12, Q14, Q17, and Q19. Accordingly, a large amount of current flows through the output load resistors R5 and R6, and thus the variable-gain amplifier yields a high gain.
On the other hand, when the levels of the input signals Vin1 and Vin2 are high, the control voltage VAGC is increased so that the base potential of the transistors Q12, Q14, Q17, and Q19 is lower than the base potential of the transistors Q13, Q15, Q16, and Q18. As a result, most of the collector current of the input transistors flows through the transistors Q13, Q15, Q16, and Q18, and almost no current flows through the transistors Q12, Q14, Q17, and Q19. Accordingly, a small amount of current flows through the output load resistors R5 and R6, and thus the variable-gain amplifier yields a low gain.
Moreover, since the control voltage VAGC is applied to the bases of the transistors Q15 and Q16, and a division voltage of the control voltage VAGC is applied to the bases of the transistors Q13 and Q18, the variable-gain amplifier circuits A1 and A2 start attenuating their gains at different threshold levels of the control voltage VAGC. Let the threshold level of the control voltage VAGC at which the variable-gain amplifier circuit A1 starts attenuating its gain be Vb1, and the threshold level of the control voltage VAGC at which the variable-gain amplifier circuit A2 starts attenuating its gain be Vb2 (Vb1 less than Vb2). The potential difference between Vb1 and Vb2 equals the potential difference between the two ends of the resistor R3.
Since the variable-gain amplifier circuits A1 and A2 are connected in parallel, the gain Gtotal of the variable-gain amplifier of FIG. 19 equals the sum of the gain GA1 of the variable-gain amplifier circuit A1 and the gain GA2 of the variable-gain amplifier circuit A2. Thus, the gain Gtotal of the conventional variable-gain amplifier with respect to the control voltage VAGC shows a characteristic curve as shown in FIG. 20. Here, in a region where the levels of the input signals are low, i.e., when the control voltage VAGC is low, the GA1 of the variable-gain amplifier circuit A1 is predominant, offering good noise figure characteristics; in a region where the levels of the input signals are high, i.e., when the control voltage VAGC is high, the GA2 of the variable-gain amplifier circuit A2 is predominant, offering good intermodulation distortion characteristics.
However, the variable-gain amplifier of FIG. 19 has the following two disadvantages. The first is the degradation of intermodulation distortion characteristics when high-frequency signals are fed in. The second is the voltage drops across output load resistors increasing as more and more variable-gain amplifier circuits are connected in parallel.
The cause of the first disadvantage, i.e., the degradation of intermodulation distortion characteristics when high-frequency signals are fed in, will be described.
In the variable-gain amplifier of FIG. 19, when the control voltage VAGC becomes higher than the threshold level Vb1 at which the variable-gain amplifier circuit A1 starts attenuating its gain, the current flowing through the transistors Q14 and Q17 decreases, attenuating the gain of the variable-gain amplifier circuit A1. However, since the constant current sources 21 and 22 supply a constant bias current IC irrespective of the level of the control voltage VAGC, the signal amplified by the input transistor Q21 is fed to the emitter of the transistor Q14, and the signal amplified by the input transistor Q22 is fed to the emitter of the transistor Q17.
When high-frequency signals are fed in, the signal amplified by the input transistor Q21 leaks through the emitter-collector parasitic capacitance of the transistor Q14 to the output load resistor R5, and the signal amplified by the input transistor Q22 leaks through the emitter-collector parasitic capacitance of the transistor Q17 to the output load resistor R6.
Thus, when high-frequency signals are fed in, even if the control voltage VAGC is increased, the gain attenuation of the variable-gain amplifier circuit A1 is saturated as shown in FIG. 21. This makes the gain difference D between the variable-gain amplifier circuits A1 and A2 smaller in a range in which the control voltage VAGC is high. When high-frequency signals are fed in, the gain attenuation of the variable-gain amplifier circuit A2 also is saturated. However, when saturated, the gain of the variable-gain amplifier circuit A2 almost equals zero, and therefore, in the following description, the gain attenuation of this variable-gain amplifier circuit A2 is assumed not to be saturated.
Now, how the smaller gain difference D degrades intermodulation distortion characteristics will be described. FIG. 22 shows the input-output characteristics of the variable-gain amplifier circuit A1, the variable-gain amplifier circuit A2, and the variable-gain amplifier as a whole. In this figure, line (1)_1 represents the input-output characteristic of the variable-gain amplifier circuit A1 with respect to the fundamental component, line (1)_3 represents the input-output characteristic of the variable-gain amplifier circuit A1 with respect to the third-order harmonic component, line (2)_1 represents the input-output characteristic of the variable-gain amplifier circuit A2 with respect to the fundamental component, line (2)_3 represents the input-output characteristic of the variable-gain amplifier circuit A2 with respect to the third-order harmonic component, line t_1 represents the input-output characteristic of the variable-gain amplifier as a whole with respect to the fundamental component, and line t_3 represents the input-output characteristic of the variable-gain amplifier as a whole with respect to the third-order harmonic component. In the graph of FIG. 22, the input level is taken along the horizontal axis, and the output level is taken along the vertical axis, with both levels given in dB.
The input level that is supposed to cause the fundamental component and the third-order harmonic component to have equal output levels is called the input intercept point (IIP3). The higher this value, the better the intermodulation distortion characteristics obtained. Let the input intercept point in the variable-gain amplifier circuit A1, in the variable-gain amplifier circuit A2, and in the variable-gain amplifier as a whole when the level of the input signal equals p be IIP3xe2x80x941(p), IIP3_2(p), and IIP3_total(p), respectively. Moreover, let the output level difference between the third-order harmonic component and the fundamental component in the variable-gain amplifier circuit A1, in the variable-gain amplifier circuit A2, and in the variable-gain amplifier as a whole when the level of the input signal equals p be IM3_1(p), IM3_2(p), and IM3_total(p), respectively.
FIG. 22 shows that the gradient of line (1)_1 is 1 and the gradient of line (1)xe2x80x943 is 3. Hence,
IIP3_1(p)=p+IM3_1(p)/2xe2x80x83xe2x80x83(1)
Moreover, FIG. 22 shows that the gradient of line t_1 is 1 and the gradient of line t_3 is 3. Hence,
xe2x80x83IIP3_total(p)=p+{D+[IM3xe2x80x941(p)]}/2xe2x80x83xe2x80x83(2)
From equations (1) and (2), IIP3_total(p) is given as
IIP3_total(p)=IIP3_1(p)+D/2xe2x80x83xe2x80x83(3)
Equation (3) shows that, to increase the input intercept point IIP3 of the variable-gain amplifier as a whole, i.e., to obtain better intermodulation distortion characteristics, the gain difference D needs to be increased. However, as described above, in the variable-gain amplifier of FIG. 19, when high-frequency signals are fed in and their levels are high, it is not possible to obtain a sufficiently large gain difference D. This leads to degraded intermodulation distortion characteristics.
Next, the cause of the second disadvantage, i.e., the voltage drops across output load resistors increasing as more and more variable-gain amplifier circuits are connected in parallel, will be described.
To make the gain characteristic curve of the variable-gain amplifier with respect to the control voltage VAGC smooth, it is advisable to connect a number of (n) variable-gain amplifier circuits in parallel as shown in FIG. 23. In FIG. 23, such circuit elements and signals as are found also in FIG. 19 are identified with the same reference numerals and symbols, and their explanations will not be repeated. The variable-gain amplifier circuits A3 to An are each configured in the same manner as the variable-gain amplifier circuit A1.
In the variable-gain amplifier of FIG. 23, through the output load resistors R5 and R6 flows n times the current that will flow through them in a configuration where only one variable-gain amplifier circuit is provided, causing, accordingly, n times the voltage drops across the output load resistors R5 and R6. Therefore, unless the resistances of the output load resistors are reduced, or the bias current IC output from the constant current sources is reduced, the transistors provided in the variable-gain amplifier may be saturated and cease to operate. However, since the amplitudes of the output signals equal the resistances of the output load resistors R5 and R6 multiplied by the current of the output signals, which are alternating currents, reducing the resistances of the output load resistors R5 and R6, quite inconveniently, results in reducing the gain of the variable-gain amplifier. On the other hand, reducing the bias current IC output from the constant current sources, also quite inconveniently, results in narrowing the input dynamic range.
An object of the present invention is to provide a variable-gain amplifier that offers a wide input dynamic range even when high-frequency signals are fed in.
To achieve the above object, according to one aspect of the present invention, a variable-gain amplifier is provided with a controller for controlling the operation of input transistors. This makes it possible to reduce the leak current that flows through transistors because of their collector-emitter parasitic capacitance when high-frequency signals are fed in and thereby prevent saturation of gain attenuation.
According to another aspect of the present invention, a variable-gain amplifier is provided with a plurality of variable-gain amplifier circuits connected in parallel and a current control circuit for controlling the bias current sources provided within each of the variable-gain amplifier circuits. This makes it possible to reduce the leak current that flows through transistors because of their collector-emitter parasitic capacitance when high-frequency signals are fed in and thereby prevent saturation of gain attenuation.